Method for generating electrically conducting and/or semiconducting structures in two or three dimensions, a method for erasing the same structures and an electric field generator/modulator for use with the method for generating

ABSTRACT

A method for generating electrically conducting and/or semiconducting structures in three dimensions in a matrix that includes two or more materials in spatially separated material structures is disclosed. An electric field is applied to the separate material structure and the field is modulated spatially according to a protocol. The protocol represents a predetermined pattern of electrically conducting and/or semiconducting structures that are generated in the material structure in response to the field. The matrix composed by the material structures includes structures of this kind in three dimensions.

[0001] A method for generating [electrical] electrically conducting [or]and/or semiconducting structures in two or three dimensions, a methodfor erasing the same structures and an electric fieldgenerator/modulator for use with the method for generating.

BACKGROUND OF THE INVENTION

[0002] The invention concerns a method for generating [electrical]electrically conducting [or] and/or semiconducting structures in two orthree dimensions in a composite matrix [, wherein the]. The matrixcomprises one or more materials provided in spatially separate andhomogenous material structures[, wherein the materials]. The materialscan undergo specific physical and/or chemical changes of state inresponse to the supply of energy [can undergo specific and/or chemicalchanges of state], which cause transition from an [electrical]electrically non-conducting state to an [electrical] electricallyconducting [or] and/or semiconducting state or vice versa, or a changein the electrical conduction mode of the of the material[, and whereineach]. Each material structure is made in the form of a thin layer.

[0003] The invention also concerns a method for [erasing] globally[electrical] erasing electrically conducting [or] and/or semiconductingstructures generated in two or three dimensions in a composite matrix[,wherein the]. The matrix comprises two or more [material] materialsprovided in spatially separate and homogenous material structures[,wherein the materials ]. The materials can undergo specific physicaland/or chemical changes of state in response to the supply of energy,[can undergo specific and/or chemical changes of state] which causetransition from an [electrical] electrically non-conducting state to an[electrical] electrically conducting [or] and/or semiconducting state orvice versa, or a change in the electrical conduction mode of the of thematerial[, and wherein each]. Each material structure is made in theform of a thin layer.

[0004] Finally, the invention concerns an electric fieldgenerator/modulator (EFGM) for patterning and generating [electrical]electrically conducting [or] and/or semiconducting structures in two orthree dimensions in a composite matrix[, wherein the]. The matrixcomprises one or more materials [respectively] provided in one or morespatially separate and homogenous material structures, [wherein the]respectively. The materials [in response to the supplied energy] canundergo specific physical and/or chemical changes of state in responseto the supply of energy, which cause transition from an [electrical]electrically non-conducting state to an [electrical] electricallyconducting [or] and/or semiconducting state [and] or vice versa, or achange in the electrical conduction mode of the of the material[, andwherein each]. Each material structure is made in the form of a thinlayer.

[0005] More particularly the present invention concerns the fabricationof two- and three-dimensional isolating, resistive, conducting [or]and/or semiconducting patterns and structures for use in electroniccircuits which most particularly consist of a single or several stackedlayers of thin films.

[0006] The evolution of microelectronic technology shows a steady trendtowards smaller dimensions and reduced costs of the devices.Well-substantiated predictions show that [the] performance is going toincrease, while the price per unit or device will decrease. However,today's microelectronic technology is substantially based on crystallinesilicon and shows an increasing tendency towards diminishing returns,mainly due to the inherent limitations associated with the complexity ofultra-high resolution lithography and increasing demands of the materialprocessing. Extrapolations of the present technologies based oncrystalline silicon [may hence] are not [be] expected to offer dramaticbreakthroughs in [regard of] either performance or price [and future].Future improvements shall require manufacturing plants and manufacturingequipment, which are extremely capital-intensive.

[0007] [Microelectronics] On the other hand, microelectronics based onthin-film technology [may on the other hand confidently be] arepredicted to deliver [in the near future] products representing realbreakthroughs in [regard of] both performance [as well as of] and pricein the near future. The shift from crystalline inorganic semiconductorsto microcrystalline, polycrystalline or amorphous inorganic or organicsemiconductors will introduce entirely novel boundary conditions withregard to the production of microelectronics [and particularly by].Particularly, the blanks [having] can have form factors, which makelarge areas possible, i.e., the substrates [may] can be large sheetsinstead of wafers cut from blanks of limited size, and great flexibilitywith regard to architectures[, something which will be]. These areessential factors in the expected development of tomorrow's electronictechnology. In the present invention special emphasis will be placed onthe use of organic materials due to the ease whereby they [may] can beprocessed [with basis in]. Additionally, organic materials allow for theuse of large areas and multilayer blanks with precisely controllablethickness, [as well as their] and provide vast potential for chemicaltailoring of the desired material properties.

[0008] [Particularly before] Before the use of electronics based onamorphous materials can [fulfil] fulfill their expected potential,further developments in certain areas are required. In [the] recentyears an effort has been made to improve the semiconducting propertiesof organic semiconducting thin-film materials[, which]. Theseimprovements have [given] caused dramatic and rapid increase in [the]transistor performance [up] to a point where organic-based transistors[may] can now compete with transistors based on amorphous silicon (seefor instance Y.-Y. Lin, D. J. Gundlach, S. F. Nelson and T. N.Jackson,“Pentacene-Based Organic Thin Film Transistors”. IEEETransactions on Electron Devices, August 1997). Other on-going projectswill lead to coating processes for thin film in order to generateorganic and amorphous silicon semiconductors at low temperatures [and]with compatibility to a broad range of organic and inorganic substratematerials. This has lead to the development of extremely [cheap]inexpensive electronic devices with large areas based on the use ofhigh-volume manufacturing methods.

[0009] In spite of this development a wholly satisfactory solution [tohow] is still lacking for adaptation of the fabrication technology[shall be adapted and made suitable for a] for low-cost flexiblehigh-volume production of electrical connections in the thin-filmstructures forming the electronic circuits [is still lacking]. Currentlythin-film devices are based on amorphous silicon manufactured withcurrent paths and conductors patterned with traditional methods such aslithography and vacuum metallization. The latter method has [formerly]also been applied to circuits for demonstration of organic-basedsemiconductor thin-film devices (see for instance A. R. Brown &al.“Logic gates made from polymer transistors and their use of ringoscillators”, Science 270: 972-974[(1995))], 1995).

[0010] Alternatively, screen printing with conducting “ink” has beenused to make transistors on flexible polymer substrates (see forinstance F. Gamier & al., “All-polymer field-effect transistor realizedby printing techniques”, Science 265: 1884-1886[(1994))], 1994). Eventhough lithography may provide high resolution, it is relatively complexand includes [typically] wet chemistry steps [which] that areundesirable in high-volume production of multilayer organic thin-filmstructures. Screen printing with ink is also far from ideal, as it onlyprovides low to moderate resolution [besides being a “wet” method.], andis a “wet” method.

[0011] [As examples of prior art such it is evident from availablepatent literature may also be mentioned U.S. Pat. No. 5,043,251(Sonnenschein & al.) which] U.S. Pat. No. 5,043,251 (Sonnenschein etal.) is an example of prior art that discloses a process forthree-dimensional lithography of amorphous polymers for generating amomentary permanent pattern in a polymer material [and which]. Theprocess comprises steps for providing doped non-crystalline layers orfilms of a polymer in a stable amorphous state under humane operatingconditions. [In manufacturing the patterns the] The film is maskedoptically and is exposed through the mask to radiation with sufficientintensity to cause ablation of the exposed portions to manufacture thepatterns such that a distinct three-dimensional imprint is generated inthe film. This process [has among other been proposed for use] is usedin the manufacture of [an] optical data storage [disk. Further it isfrom U.S. Pat. No. 5,378,916 (Mantell) known a photo-sensitive] disks.Further, U.S. Pat. No. 5,378,916 (Mantell) discloses a photosensitivedevice in the form of a single-crystal structure, wherein differentportions of the structure may have different compositions. [Particular]Particularly, the structure forms a two-dimensional array [and a]. Afirst photosensitive portion comprises a material, which generateselectron-hole pairs when it is exposed to light within a predeterminedfirst wavelength range, while another photosensitive portion comprises amaterial which is adapted to generate electron-hole pairs when it isexposed to light within another wavelength range distinctively differentfrom the first wavelength range. [Yet further it is from U.S. Pat. No.5,677,041 (Samyling) known] Still further, U.S. Pat. No. 5,677,041(Smayling) discloses a transistor device [which] that is made by forminga doped layer of radiation-sensitive material on a substrate. Theradiation-sensitive material may among others be polyimid, polymer, anorganic dielectric, a conductor or a semiconductor. The substrate [may]can be silicon, quarts, gallium arsenide, glass, ceramic, metal orpolyamid. A neutral or undoped layer of another radiation sensitivematerial is formed over the doped layer. First and second source/drainareas are then formed in the neutral layer and extend down to a topportion of the doped layer. A gate area is formed in the top portion ofthe neutral layer between the first source/drain area and the secondsource/drain area such that a channel area in the doped layer isprovided under the gate area. Drain/source and gate electrodes [as] areformed by irradiation of the uppermost neutral layer through a maskpatterned in accordance with the desired electrode pattern and realizedsuch that it intensity-modulates the radiation. In addition the mask mayalso be realized as a phase-shifting mask.

[0012] Finally [it is from], the article, “Polymeric integrated circuitsand light-emitting diodes” of D. M. de Leeuw & al., IEDM, pp. 331-336(1997) [known], discloses a [ ]MISFET wholly realized in polymer [andwith the use of]. The polymer materials [which] are given the desiredelectrical properties by [an] exposure to UV radiation. In themanufacture photochemical patterning of doped [electrical] electricallyconducting polyaniline films, so-called PANI thin films is used. [The]After the films are dissolved in a suitable solution, [whereafter] aphoto-initiator is added to the solution [which] that has been depositedon a suitable substrate, such as a polyimide film. [By thereafter] Afterexposing the PANI film to deep UV radiation through a mask, theinitially conducting polyaniline is converted [in the exposed areas] tothe non-conducting leucoemeraldine form[. The] in the exposed areas.Accordingly, the starting point [here] is [accordingly] a conductingpolymer material[, the]. The area resistance of [which] the material isinitially [is] 1 kiloohm/square[, but which after]. After the exposure,the material obtains an area resistance of more than 10¹³ ohm/square. Inthis manner, dielectric structures [may] can be generated in anotherwise conducting matrix. FIG. 1 shows a MISFET according to Leeuw[&] et al. comprising a polyimide substrate 1 with a PANI thin film[which after]. After exposure to UV light through suitable masks[forms], isolating structures 6 are formed in the otherwise conductingthin-film material 3. The still conducting areas 3 in the PANI filmdefine [respectively] the source and drain electrode of a MISFETtransistor, respectively. Above the PANI film a further layer 4 isdeposited in the form of a thin film of polythienylenevinylene or PTV[which] that is an organic semiconductor material. This layer 4substantially determines the electrical parameters of the MISFETtransistor. A film 5 of polyvinyl phenol PVP [which] that is opaque toUV radiation and visible light forms the gate isolator of the transistorand is [opaque to UV radiation and visible light is] deposited over thePTV film 4. [ ]Another PANI film is [again] deposited on the top of thePTV film 5 and is patterned by radiation with UV light such thatisolating structures 6 are formed. A still [electrical] electricallyconducting area 2 forms the gate electrode of the MISFET structure.

[0013] If several transistors of [this] the kind [as] mentioned above[shall be] are combined in integrated circuits [realized] in the form ofstacked film layers, vertical current paths [between for instance ]mustbe used. For instance, vertical current paths can exist between sourceand drain electrodes in a transistor and the gate electrode in anothertransistor [must be used]. Such vertical current paths [may inprinciple] can be realized mechanically, for instance, by depositing ametal film over vertically etched steps in the structure. [Otherwise aclose analogy is the use of] The throughplated holes in a circuit[boards] board for [realizing] forming a vertical connection betweencurrent paths on the upper and lower side of the circuit board areanalogous to the vertical current paths.

SUMMARY OF THE INVENTION

[0014] An[. The main] object of the present invention is to provideimproved [fabrication] methods [for] of fabricating conductingconnections and electrodes in microelectronic components and[particularly] microelectronic devices with large areas on flexiblesubstrates [by means of processes which combine]. The method furtherprovides high-volume fabrication at low costs. Particularly, it is anobject of the invention to provide [such] fabrication methods that [theymay] can be used on layered physical devices, for instance [in the formof], three-dimensional circuit structures formed by a large number ofadjacent stacked thin-film layers[, thus generating three-dimensionalcircuit structures. The present invention will thereby make possibleflexible and cheap, but simultaneously also singularly]. Thus, thepresent invention provides flexible, inexpensive, simple and precisefabrication of devices such as flat display devices, logic circuits,memory devices [etc], and the like.

[0015] Further, it is also an object of the invention to provide amethod for erasing such three-dimensional circuit structures in situ,such that the material in the structures is converted back to an initialvirgin state [whereafter it]. After the erasing process, the material bymeans of a suitable method [may] can be reconfigured in the form of[electrical] electrically conducting [and] and/or semiconductingstructures in three dimensions, [but] for instance with another patternor another structure than the original. the uppermost neutral layerthrough a mask patterned in accordance with the desired electrodepattern and realized such that it intensity-modulates the radiation. Inaddition the mask may also be realized as a phase-shifting mask.

[0016] Finally [it is from], the article, “Polymeric integrated circuitsand light-emitting diodes” of D. M. de Leeuw & al., IEDM, pp. 331-336(1997) [known], discloses a [ ]MISFET wholly realized in polymer [andwith the use of]. The polymer materials [which] are given the desiredelectrical properties by [an] exposure to UV radiation. In themanufacture photochemical patterning of doped [electrical] electricallyconducting polyaniline films, so-called PANI thin films is used. [The]After the films are dissolved in a suitable solution, [whereafter] aphoto-initiator is added to the solution [which] that has been depositedon a suitable substrate, such as a polyimide film. [By thereafter] Afterexposing the PANI film to deep UV radiation through a mask, theinitially conducting polyaniline is converted [in the exposed areas] tothe non-conducting leucoemeraldine form[. The] in the exposed areas.Accordingly, the starting point [here] is [accordingly] a conductingpolymer material[, the]. The area resistance of [which] the material isinitially [is] 1 kiloohm/square[, but which after]. After the exposure,the material obtains an area resistance of more than 10¹³ ohm/square. Inthis manner, dielectric structures [may] can be generated in anotherwise conducting matrix. FIG. 1 shows a MISFET according to Leeuw[&] et al. comprising a polyimide substrate 1 with a PANI thin film[which after]. After exposure to UV light through suitable masks[forms], isolating structures 6 are formed in the otherwise conductingthin-film material 3. The still conducting areas 3 in the PANI filmdefine [respectively] the source and drain electrode of a MISFETtransistor, respectively. Above the PANI film a further layer 4 isdeposited in the form of a thin film of polythienylenevinylene or PTV[which] that is an organic semiconductor material. This layer 4substantially determines the electrical parameters of the MISFETtransistor. A film 5 of polyvinyl phenol PVP [which] that is opaque toUV radiation and visible light forms the gate isolator of the transistorand is [opaque to UV radiation and visible light is] deposited over thePTV film 4. [ ]Another PANI film is [again] deposited on the top of thePTV film 5 and is patterned by radiation with UV light such thatisolating structures 6 are formed. A still [electrical] electricallyconducting area 2 forms the gate electrode of the MISFET structure.

[0017] If several transistors of [this] the kind [as] mentioned above[shall be] are combined in integrated circuits [realized] in the form ofstacked film layers, vertical current paths [between for instance ]mustbe used. For instance, vertical current paths can exist between sourceand drain electrodes in a transistor and the gate electrode in anothertransistor [must be used]. Such vertical current paths [may inprinciple] can be realized mechanically, for instance, by depositing ametal film over vertically etched steps in the structure. [Otherwise aclose analogy is the use of] The throughplated holes in a circuit[boards] board for [realizing] forming a vertical connection betweencurrent paths on the upper and lower side of the circuit board areanalogous to the vertical current paths.

SUMMARY OF THE INVENTION

[0018] An[. The main] object of the present invention is to provideimproved [fabrication] methods [for] of fabricating conductingconnections and electrodes in microelectronic components and[particularly] microelectronic devices with large areas on flexiblesubstrates [by means of processes which combine]. The method furtherprovides high-volume fabrication at low costs. Particularly, it is anobject of the invention to provide [such] fabrication methods that [theymay] can be used on layered physical devices, for instance [in the formof], three-dimensional circuit structures formed by a large number ofadjacent stacked thin-film layers[, thus generating three-dimensionalcircuit structures. The present invention will thereby make possibleflexible and cheap, but simultaneously also singularly]. Thus, thepresent invention provides flexible, inexpensive, simple and precisefabrication of devices such as flat display devices, logic circuits,memory devices [etc], and the like.

[0019] Further, it is also an object of the invention to provide amethod for erasing such three-dimensional circuit structures in situ,such that the material in the structures is converted back to an initialvirgin state [whereafter it]. After the erasing process, the material bymeans of a suitable method [may] can be reconfigured in the form of[electrical] electrically conducting [and] and/or semiconductingstructures in three dimensions, [but] for instance with another patternor another structure than the original.

[0020] The above-mentioned features and advantages are realizedaccording to the present invention with a method which is characterizedby applying to [the] a separate layer an electric field with given fieldstrength and/or characteristics adapted to the specific response of thematerial to the energy supplied by the field[, modulating in]. In eachcase the fields are modulated spatially according to a determinedprotocol which represents a predetermined pattern of [electrical]electrically conducting [or] and/or semiconducting structures in therelevant material structure[, whereby in the layers in]. In response tothe energy supplied by the field two-dimensional [electrical]electrically conducting [or] and/or semiconducting structures aregenerated in the layers with the pattern predetermined by the protocol[,and then optionally providing]. Then, two or more layers are optionallyprovided in a stacked configuration, such that the composite matrixformed by separate adjacent layers is provided with [electrical]electrically conducting [or] and/or semiconducting structures in threedimensions.

[0021] Further, it is [according to the invention] advantageous that theelectric field is modulated spatially in a plane substantially parallelwith a layer by means of an electrode device with patterned electrodes[,the electrode device by]. By selective supply of voltage to theelectrodes according to the determined protocol [generating], theelectrode device generates electrical point or line potentials, whichgenerate the [electrical] electrically conducting [or] and/orsemiconducting structures.

[0022] [It is according to invention advantageous that the stackedconfiguration is formed by two or more layers] According to anotheraspect of the invention, after generating the [electrical] electricallyconducting [or] and/or semiconducting structure in each layer [being],it is advantageous that two or more layers form a stacked configuration.Each layer is combined into laminated multilayer structures [whichforms] that form the composite matrix with [electrical] electricallyconducting [or] and/or semiconducting structures in three dimensions.

[0023] [It is according to ]According to yet another aspect of theinvention [also], it is advantageous to positioning the multilayerformed by a lamination of two or more self-supporting layers into astacked configuration. [A layer is after] After the lamination toadjacent layers, a first layer is then preferably positioned such thattwo or more two-dimensional [electrical] electrically conducting [or]and/or semiconducting structures in the first [-mentioned] layeraccording to the protocol register with one or more two-dimensional[electrical] electrically conducting [or] and/or semiconductingstructures in adjacent layers[, whereby]. Thus, one or more vertical[electrical] electrically conducting [or] and/or semiconducting channelsare generated in the cross-direction through the layers.

[0024] Finally, it is according to the invention advantageous providingan [electrical] electrically conducting [or] and/or semiconductingstructure which forms a vertical channel through the layer according tothe protocol, in [electrical] electrically conducting [or] and/orsemiconducting connection with one or more two-dimensional [electrical]electrically conducting [or] and/or semiconducting structures in thislayer[, each]. Each channel preferably [being] is generated with aconductivity or conduction mode which is constant between the layers orwith a conductivity or conduction mode which varies between the layers.

[0025] A method for global erasing according to the invention ischaracterized by applying globally to the composite matrix an electricfield with given field strength and/or characteristics adapted to thespecific response of the material to the energy supplied by the fielduntil the materials in their entirety arrive in the electricallyconducting and/or non-conducting state in the composite matrix inresponse to the energy supplied by the field [in their entirety arrivein the electrical or non-conducting state.].

[0026] [An] According to the another embodiment of the invention, anelectric field generator/modulator [is according to the inventioncharacterized in that it] comprises a first electrode means with aplurality of parallel strip electrodes provided in a plane[, a]. Asecond electrode means with a plurality of parallel strip electrode s isprovided at a distance from the first electrode means andsuperpositioned thereto in a second plane parallel with the first planesuch that the electrodes mutually are substantially orthogonallyoriented in a matrix-like arrangement[, that the]. The electrode means[over cross-connection devices] are connected with a controllable powersupply[, the electrical field generator/modulator in the] overcross-connection devices. The space between the electrode means [being]in the electrical field generator/modulator is adapted for receiving athin-film material in the form of a discrete component or a continuoustape [which without touching the electrode means continuously orintermittently]. The thin film material is fed through the space withouttouching the electrode means continuously or intermittently, and withsimultaneous positioning and alignment spaced apart from and between theelectrode means in a plane substantially parallel thereto[, whereby theelectrical]. The electrically conducting [or] and/or semiconductingstructures can be generated according to a determined protocol [and] bymeans of point, line or area potentials [is] created between selectedelectrodes in the electrode means when [the former] electrodes aresupplied with electric power over the cross-connection devices [aresupplied with electric power]. Preferably [are], the electrodes in eachelectrode means are provided on or in surfaces of respective substratesfacing each other and/or [in that connection] preferably are made as apart of the substrates and form conducting structures in the substratematerial.

[0027] Further it is according to the invention advantageous that thedistance between the electrode means is controllable depending on thethickness of the thin-film material.

[0028] Finally, it is according to the invention advantageous that theelectrodes in each electrode means are provided with a mutual distancebetween 0.1 μm and 1.0 μm and that the electrodes in each electrodemeans are formed with substantially constant width of 0.1 μm to 1.0 μm.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The invention shall now be explained in more detail in connectionwith a survey of its basic principles and with the use of exemplaryembodiments in connection with the appended drawings, wherein

[0030]FIG. 1 shows a MISFET with the electrodes formed ofphotoconvertible material according to prior art[,];

[0031]FIGS. 2a, b schematically respectively in section and plan view anembodiment of the electric field generator/modulator (EFGM) according tothe invention and its use in a first step in the method for generatingaccording to the invention[,];

[0032]FIGS. 2c, d schematically in respectively section and plan viewEFGM as shown in FIGS. 2a, b and used in a second step in the method forgenerating according to the invention[,];

[0033]FIGS. 2e, f schematically in respectively section and plan viewEFGM as shown in FIGS. 2a, b and used in a third step of the method forgenerating according to the invention [,];

[0034]FIG. 3 schematically the embodiment of the method for generatingaccording to the invention, combined with a lamination of single layersinto a multilayer structure[,];

[0035]FIG. 4 a section through a multilayer structure with conducting[and] and/or semiconducting structures as generated by the steps shownin FIGS. 2a-f, FIG. 5 a schematic section through a laminated multilayerstructure which comprises conducting or semiconducting structuresgenerated by the method according to the present invention[,];

[0036]FIG. 6 a schematic section through a diode structure generated bythe method according to the present invention[,];

[0037]FIG. 7 a schematic section through a MOSFET structure generated bythe method according to the present invention[,];

[0038]FIG. 8 a schematic section through a logic inverter structurebased on the MOSFET structure in FIG. 7 and generated by the methodaccording to the present invention[,];

[0039]FIG. 9 the equivalent diagram of an AND gate realized in CMOStechnology[,];

[0040]FIGS. 10a-d in plan view sublayers in an AND gate structuregenerated by the method according to the invention and according to theequivalent diagram in FIG. 8 with the use of MOSFET structures as shownin FIG. 7[,];

[0041]FIG. 11 the AND gate structure in FIG. 10 as a stacked multilayerconfiguration, but exploded in the separate sublayers; and[,]

[0042]FIG. 12 schematically another variant of the AND gate structure inFIG. 10 and with the separate MOSFET structures provided mutuallyconnected in a vertical configuration.

DETAILED DESCRIPTION OF THE INVENTION

[0043] Now the basic principles of a method according to the presentinvention whereby three-dimensional structures with a well-defined modeand degree of electrical conduction are generated by spatiallycontrolled patterning in situ in convertible materials (CM) [which havesuch]. The convertible materials have properties such that theirelectronic properties are converted reversibly or irreversibly under theeffect of radiation, heat, or electric fields. The method for generatingsuch structures according to the present invention is based on the useof electric fields, either direct current fields or alternating currentfields. Initially the three-dimensional [electrical] electricallyconducting [or] and/or semiconducting structures can be generated astwo-dimensional structures [of this kind]. The as two-dimensionalstructures are generated by direct local influence of the electric fieldon a single layer [and appears as three-dimensional by joining]. Joiningsingle layers into a multilayer structure forms three-dimensionalstructures. Typically an electric field-convertible material (EFCM) willbe an organic material, for instance a molecule, an oligomer or apolymer where a phase transition from an initial first state to a newsecond state takes place upon being subjected to an electric field[, forinstance] of a given field strength or with a given frequency.

[0044] As mentioned in the following, it is presupposed that the mostimportant change taking place from the first to the second state, is thedegree of electrical conduction. In the following, the method forgenerating and erasing [of electrical] electrically conducting [or]and/or semiconducting structures by means of electric fields shall bediscussed both generally and more specifically in connection with adescription of the figures.

[0045] For polymers such as polyaniline [there are ]conduction ratiosbetween two states are observed as high as 10¹⁰, as shown in theabove-mentioned paper by de Leeuw & al.[, observed conduction ratiosbetween two states as high as 1010. In this case it concerned] Thispaper addressed in situ conversion of a single layer of irradiationconvertible material from conducting to non-conducting state in order togenerate electrical connections in a single electronic circuit.[Electrical] Electrically conducting connections in doped polyanilinefilms (PANI films) were defined by exposure to deep UV radiation througha patterned mask.

[0046] A multilayer stack of different electric field-convertiblematerials [may] can be provided on a substrate, which [may] can beflexible or rigid, and conducting or non-conducting. Thefield-convertible material [are] is made conducting, semi-conducting orisolating (i.e., non-conducting) in desired patterns by subjecting anumber of single layer field-convertible materials tospatially-controlled electric fields[, and with subsequent combinationof]. Subsequently, the layers can be combined into a multilayer stack.Multilayer stacks of field-convertible material are of particularinterest in connection with multilayer thin-film circuits where it isrequired to generate [electrical] electrically conducting lines, currentpaths, connection points or electrodes in several layers such that theconducting structures in one layer has a precisely controlled spatialrelationship to the conducting structures in the layers which arelocated above or below. One example is thin-film field effecttransistors (TFET) where the source and drain electrode in a layer mustbe correctly positioned relative to the gate electrode, and [with]intervening isolating and semiconducting layers. Another example iselectrical connections between the layers where traditional solutions inmany cases are unsatisfactory[, for]. For instance [by incorporating], anumber of steps such as forming open channels or vias between suitablepoints, which then shall be electrically connected in the differentlayers [and], can be incorporated with subsequent filling or casing ofthe channels with a conducting material[, such as this finds itsparallel in]. This is analogous to the use of through-plated holes incircuit boards to obtain a connection from the front to the back of thecircuit board. [A third instance is the generation of] In anotherexample, capacitors are formed by defining conducting areas, which arealigned mutually opposite in two layers separated by an isolating layer.[Evidently not only highly] Highly conducting, [but also] isolatingresistive and semiconducting patterns in multilayer structures are allaspects of the [greatest importance. Such as] present invention. As willbe explained in more detail in the following, patterns of this kind[may] can be generated by using the method for generating [electrical]electrically conducting [or] and/or semiconducting structures orpatterns according to the present invention. [With regard to theprecision and clarity the] The following description [shall, however. beintroduced by emphasizing on] emphasizes how patterns andthree-dimensional structures are defined, which [either] are [very] goodor [very bad] poor electrical conductors [shall be defined].

[0047] Multilayer structures as described herein are of particularinterest when they are integrated with thin-film semiconductors in orderto form complete circuits. [The present standard] Conventionalprocedures for fabricating microelectronic circuits, which exploit thesemiconducting properties of a common silicon substrate, restrictautomatically the realizable architectures to the kind [which] thatallows access to the substrate for all active devices. If the methodaccording to the present invention is used for generating [electrical]electrically conducting [or] and/or semiconducting structures in threedimensions by means of converted single stacked single layers, thenwhole devices [may] can be generated in [this manner] without anyessential restriction with regard to the size or complexity [as] becausescaling [quite] simply takes place by joining more layers to the stack.[As] Since each layer [may] can be made thin, for instance with an orderof magnitude of 10-100 μm, the resulting volumetric density for thecircuit patterns and hence the performance per weight or volume unit[may] can be extremely high. Further, hybrid architectures [may] can berealized with the use of layers which [includes] include electricalfield-converted electronic structures which are formed on the top of andfunction in cooperation with traditional silicon-based electroniccircuits.

[0048] [The basic] An object of the present invention is the generationof [electrical] electrically conducting, semiconducting or resistivestructures in three dimensions within a multilayer material inmonolithic format[, as the]. The structures [mentioned] are generated[with the use of] by electric fields in the form of point, line or areapotentials. An embodiment of the method [for generating with the use ofelectric field shall now be] is now described with reference to FIGS.2a-f.

[0049]FIG. 2a shows a section through an electric fieldgenerator/modulator according to the invention [which] that functions asan electric patterning device for electric field-convertible materials.The electric field generator/modulator is realized such that it bothgenerates the field and [in addition also can modulate] modulates thefields spatially, [i.e.] i.e., in a plane or two-dimensions [andgenerate electrical], thereby generating electrically conducting [or]and/or semiconducting structures with the desired pattern in this plane.In the following [will hence], the electric field generator/modulator[abbreviated be] is denoted as EFGM. [EFGM 20 comprises as] As shown inFIG. 2a in section and in FIG. 2b in plan view, EFGM 20 comprises afirst electrode means E1, consisting of thin parallel electrodes 21 andanother electrode means E2 provided spaced apart from the electrodemeans E1 in a plane parallel thereto. The electrode means E2 consistssimilarly of thin parallel electrodes 22 provided such that they areoriented substantially orthogonal to the electrodes 21 in the electrodemeans E1. The electrode means E1, E2 are connected with a power supply23 [, here] shown as a direct voltage power supply[, but]. However, thepower supply 23 may also be an alternating voltage power supply. Thepower supply 23 is connected with the electrode 21 [;], 22 in theelectrode means E1 [;], E2 over respective cross-connecting devices[21,24] 24, 25. The distance between the electrode means E1, E2 allows athin film of electrical field-convertible material EFCM, in FIG. 2adenoted as SS1, to be inserted between the electrode means E1, E2,without contacting these electrodes. The electrode means E1, E2 [may]can be formed of self-supporting or supported thin films, wherein theelectrodes 21,22 in each case are embedded in the film material.Similarly [it is to be understood that], the layer SS1 of thefield-convertible material EFCM [may] can be a continuous tape [which]that is inserted in EFGM 20 between the electrode means E1, E2 in asubstantially continuous movement. By applying voltage [e.g.], to anelectrode 21 in the electrode means E1 and to an electrode 22 in theelectrode means E2, an electric field perpendicular to the layer SS1 isformed in the intersection between the electrodes 21 and 22 [and the].The field-convertible material SS1 [will be able to transfer] cantransform from a non-conducting to a conducting state in areas [whichis] that are influenced by the field between the electrodes [21,22] 21,22. If an electrode 21 and another electrode 22, respectively, areaddressed electrically in this manner, an approximate point potential isobtained in the intersection between. [If e.g.] For example, if anelectrode 21 in the electrode device E1 and all electrodes 22 in theelectrode device E2 are addressed, a field is obtained substantially inthe form of a line potential along the electrode 21 in question [andcorrespondingly]. Correspondingly, a line-like structure will begenerated, for instance an [electrical] electrically conductingstructure in the layer SS1 which is located between the electrodedevices E1, E2 [will be generated]. If [an] a number of electrodes 21[which] that are located juxtaposed to each other in the electrodedevice E1 and correspondingly a plurality of electrodes 22 which arejuxtaposed to each other in the electrode device E2, the field [whichare] created between the electrode intersections [will generate]generates an area potential [and it may for]. For instance [begenerated], an electric area structure can be generated in the layer SS1by this field. In FIGS. 2a, 2 b [such electrical], these electricallyconducting structures are [e.g.] generated substantially as areastructures[, but it is to be understood that there also may be generatedas point of line structures, dependent]. However, point or linestructures can be generated depending on the manner whereby the electricfield is generated.

[0050]FIGS. 2c and 2 d show respectively in section and plan view howEFGM 20 is used for generating [for instance electrical] electricallyconducting structures 9 in a second layer by addressing the electrodemeans E1, E2 in EFGM 20 in a suitable manner. Correspondingly, FIGS. 2e,f [also shows] show in section and plan view EFGM 20 with a third layerSS3 [which here for instance]. Layer SS3 is patterned withsemiconducting structures 10. As shown in [FIG.] FIGS. 2a-f, thepatterning of the field-convertible material EFCM takes place for eachseparate layer SS1, SS2, SS3. [but these layers may] However, asmentioned above[,] these layers can be present in the form ofself-supporting single films of EFCM and assembled into a multilayerstack, [such this] which schematically is shown in FIG. 3. Thefabrication of circuits realized with [electrical] electricallyconducting [and] and/or semiconducting structures in EFCM can take placewith tapes of EFCM in continuous paths as shown. Each tape or each film[are], shown in FIG. 3 [shown] as three films EFCM1, EFCM2[.], EFCM3[and are], is converted by electric field to the desired spatial patternin a separate EFGM 20 for each of the paths. Then [follows theassembly], the layers are assembled into a multilayer structure MLS, [e.g.] e.g., by gluing or heat-assisted lamination. The multilayerstructure MLS [may well] can be provided on a substrate [which, ofcourse,] that is not subjected to any electric field[, but]. However,the substrate is laminated to the multilayer structure MLS in the sameprocess step. In each case a flexible tape MLS is obtained [which] thateither [may] can be folded [or], coiled or cut into segments, forinstance, to make single circuits. In FIG. 3, the field-convertiblematerial EFCM in the form of three tapes or films EFCM1, EFCM2, EFCM3 isdrawn from respective rolls [R3] R_(a) and conveyed in separate lines byalignment rolls R_(b1), R_(b2), R_(b3), R_(b4) in each line fortensioning and positioning of the tapes through EFGM 20. The completedpatterned films EFCM1, EFCM2, EFCM3 are conveyed over a guide roll set[Re and possibly] R_(c). Possibly after a further position adjustment[through], a lamination step R_(d) [and laminated] laminates thecompleted patterned films EFCM1, EFCM2, EFCM3 into the multilayerstructure MLS. This multilayer structure [may as mentioned,] can includea substrate 1, which is drawn from a further roll R_(a) in a separateline[} and]. The substrate 1 is laminated together with the convertedfilm material EFCM in the lamination step R_(d). [For three] Threelayers, which are laminated together in this manner and converted asshown in [FIG.] FIGS. [ ]2 a-f, [it may then as shown] can berepresented schematically in section view as shown in FIG. 4 [beobtained a]. A circuit structure [which] is thereby provided on thesubstrate 1. The conducting structures 9 and the semiconductingstructures 10 contact each other vertically or extend horizontally ineach of the layers SS1, SS2, SS3 as shown [and form together]. Together,the conducting structures 9 and the semiconducting structures 10 formthree-dimensional structures [of this kind] in the desired pattern.

[0051] The electrode means E1, E2 in the electric fieldgenerator/modulator (EFGM 20), as [for instance] shown in FIG. 2a andFIG. 2b, [may] can be formed in or on substrates of a non-conductingmaterial [and the]. The electrodes 21, 22 [may then] can be provided onthe opposite surfaces of the substrates or embedded in the substrates.They may also form conducting structures in the substrate materialitself. The electrode width and the mutual distance between theelectrodes 21, 22 in each electrode means E1, E2 [will be determining]is determined for the spatial resolution in the patterning of theconducting or semiconducting structures and the achievable pitches. Incompatibility with today's semiconductor technology, the electrodes 21,22 [thus] can be realized with a width between 0.1 and 1.0 μm andcorresponding mutual distances. It is [with present technology whollypossibly] possible to realize electrode widths, [e.g.] e.g., in thinfilms provided on substrates, of 0.1 μm or less by nanotechnology[, forinstance] printing methods, or by means of chemical methods. The circuitpatterns [which]that are realized with EFGM20 [with the method]according to the present invention [will] are at least [be]dimensionally compatible [with that which optimally may be] thoseachieved by using [for instance] microlithography in silicon-basedcircuit technology[. Dependent], for instance. Depending on thethickness of the thin film material wherein conducting or semiconductingstructures[, i. e.] (i.e, circuit patterns[, shall be]) are generated,the distance between the electrode devices E1, [ ]E2 can be controlled[in order] to achieve an optimum definition of the potentials formedbetween the electrodes. The control may take place via [not shown]micromechanical servocontrol means (not shown), which are well-known topersons skilled in the art. [−]During the generation of the circuitpattern, the space between the electrodes [may besides] can be filledwith an isolating gas with high dielectric strength in order to prevent[break-down] breakdown between the electrodes.

[0052] The power supply 23 in EFGM 20[, e. g.] (e.g., as shown in FIGS.2a and 2 b[,]) may either be a direct current source or an alternatingcurrent source. Preferably [it will be realized as], power supply 23 isa controlled power supply and [be] able to supply the electrode meansE1, E2 with current with different modes and characteristics. For thispurpose both the power supply 23 and the cross-connection means 24, 25[hence will] can be connected with [a not shown] an external controldevice [which may](not shown) that can be programmed according to theprotocol for a desired circuit pattern and corresponding control thegeneration of the desired [electrical] electrically conducting [or]and/or semiconducting structures in the layer material or the thin filmmaterial between the electrode means E1, E2. Protocols and requiredsoftware [may] can be loaded to the [not shown] control device (notshown) from any external source [and it is hence nothing against that].Therefore, the fabrication of circuits [with the use of] using EFGM 20[may] and the above method can be managed from a distant locality.

[0053] [There shall now be given a more] A detailed discussion of theelectric field-convertible materials EFCM [which may] that can be usedin the method according to the present invention[, as well as] andspecific techniques [which may] that can be used in [the] an embodimentof said method follows. The basic principle of in situ field-conversionof materials is to generate conducting or semiconducting structures bymeans of spatially modulated and/or field strength modulated electricfields. [The] Additionally, the conversion itself may [additionally] bereversible or irreversible. Concrete examples [of this will be givenbelow. It must be mentioned that EFCMs at the time being] are providedbelow. EFCMs are in an early development stage [and it]. It is [to be]expected that ongoing research and development activities in [the] thisfield will dramatically [shall] increase the number of availablematerials.

[0054] [It is in] In the present invention, it is particularly preferred[using] to use EFCMs which by being subjected to an electric fieldremain in [this state ]an altered state (e.g., conducting and/orsemiconducting) until they again are subjected to a field which bringsthe material back to the initial state (e.g., non-conducting). This is[among other] the case of different organic macromolecules and othermaterials [which] that generally are known as molecular electronicmaterials. [An instance of a] A material of this kind is disclosed inthe paper “A new material for optical, electrical and electronic thinfilm memories” by Z. Y. Hua & G. R. Chen, Vacuum, Vol. 43, No. 11:1019-1023 (1992). This material is an organometallic charge-transfercomplex M (TCNQ) formed by TCNQ [(7,7,8,8-tetracyanoquinodimetan,C12,H4N4)](7,7,8,8tetracyanoquinodimetan, C₁₂H₄N₄) which functions as anelectron acceptor molecule with different metals as electron-richdonors. The metals [may] can be Li, Na, K, Ag, Cu or Fe. M (TCNQ) may[under] transfer from a high impedance state to a low impedance state inresponse to the application of electric fields [and for the sake of thatalso] or energy supplied in the form of heat or light radiation[transfer from a high impedance state to a low impedance state].Generally the reaction can be written as

[M⁺(TCNQ)⁻ ]n←e^(by,E→)Mx+(TCNQ)x+[M⁺(TCNQ)⁻]n−x

[0055] The process is reversible, as the return reaction [may] can beobtained by supplying energy ε in the form of heat, electrical fields orphoton radiation. [The] Because of the reversible reaction [results inthat], M (TCNQ) [may] can be used for generating a bistable switchingmedium, [for instance] such as an erasable memory material. [In themethod] Only electric fields are used in methods according to thepresent invention [only electric fields are used and not irradiation].Irradiation is not used. In thin layers, for instance of 100-200 nm, M(TCNQ) has non-liner current-voltage characteristics, [something] which[may] can be used for realizing memories of the type ROM and RAM. [Forthis purpose it] It is of particular interest that M (TCNQ) stably and[reproducably] reproducibly allows current-controlled bistableelectrical switching. [In an electrical] For instance, in anelectrically addressable memory [for instance], the high impedance state[may be used for representing] can represent binary 1 and the lowimpedance state binary 0. The transition time between two such states isless than 400 ns. [−]Further examples of relevant materials arediscussed in W. Xu & al., “Two new all-organic complexes with electricalbistable states”, Appl. Phys. Lett. 67: 2241-2242 (1995) and the[therein] appended literature references therein. The materialsmentioned are bistable and have well-defined thresholds for conversionfrom conducting to [nonconducting] non-conducting state and vice versawith the use of electric fields.

[0056] In certain field-convertible materials, including TCNQ, theconversion from a non-conducting to a conducting state may also takeplace when the energy is supplied in the form of the heat. As thefield-convertible material basically is dielectric or stronglyresistive, an electric alternating field applied via the electrodes[which over the electrodes is applied ] with a suitable frequency to thematerial[,] may induce heat in the potential area [and a]. The heating[with] causes a subsequent conversion of the material from anon-conducting to a conducting state in this area [may then take place].The power supply [must] is then [be] operated as an alternating powersupply and the thermal conversion [must be] is regarded as a secondaryeffect induced by the electric field. In order to obtain good spatialdefinition of the generated [electrical] electrically conducting [or]and/or semiconducting structures, the thermal field [which is] inducedby the alternating field in the material [must be] is preciselycontrolled. The thermal field will [namely] propagate through thematerial and cause a temperature increase [which] that may influence theelectrical properties of the material outside the potential area [whichideally shall define]. Ideally the potential area defines the spatialextent of the generated structure. If the field-convertible material isregarded as an infinite thin layer, the temperature increase [will makeitself felt unto] extends a distance from [for instance] a pointpotential which falls together with the intersection point of theactivated electrodes, with a thermal diffusion length defined by theformula

μ=(κ/πfpc)^(½)  (1)

[0057] where the material parameters

[0058] κ=thermal conductivity,

[0059] f=1/τ the characteristic frequency which is

the inverse of the pulse duration τ,

[0060] p=the density of the material, and

[0061] c=the specific heat of the material.

[0062] It follows from equation 1 that in order to reduce the thermaldiffusion and obtain a sharp spatial definition of the desired[electrical] electrically conducting or semiconductor structures, analternating current pulse should be used which provides high fieldstrength and a fast temperature increase in the potential area withsubsequent rapid conversion of the field-convertible material. This[may] can be achieved by combining a high field strength with high fieldfrequency and with the use of field-convertible materials in the form ofthin films with a thickness of 100 nm [it is supposed that an].Effectively, unwanted thermal diffusion [effectively] can be avoided byusing alternating current pulses of at most a few microseconds. [In thisconnection the] The field characteristics [must] are also [be] tuned tothe desired degree of conductivity on the potential areas, which ideallydefines the generated conducting [and] and/or semiconducting structures.

[0063] Electrical connections between different layers in thin-filmmaterials or other types of electronic materials present a majorchallenge for the fabrication of microelectronics. Precise positioningof conducting paths in each layer plane and in the perpendiculardirection to the planes is of paramount importance and comprisestypically forming vias or holes which [may] can be filled withconducting material in order to create connections perpendicular to thelayers. The physical manufacture of the holes in the prior art takesplace by means of drilling, punching or etching, and the conductingmaterial is added by mechanical filling, electroplating, etc. Veryclearly processes of this kind represent a significant complication anda substantial cost with an accompanying limited precision.

[0064] In the present invention the connections, as well as active andpassive devices [may], can be generated in the same processing sequencewhich defines the [electrical] electrically conducting [and] and/orsemiconducting structures in each layer, [i.e.] i.e., with the same kindof spatial precision as the structures themselves and without resortingto further and other types of manufacturing steps. FIG. 5 shows thebasic principle for the particular case where a single conducting path 9shall be generated between a portion of [for instance of] a conductingstructure in a layer SS5 and a portion of another conducting structure 9in a layer SS8 spaced apart from the former. By repeated conversion of asmall area in the same location of [in] each of several adjacent layersbetween the termination points of a conducting or semiconductingstructure, a column [9′of] 9′ of conducting material is formed as shownin FIG. 5 [and electrical]. Electrical conductivity is obtained stepwisefrom the starting layer SS5, which contains the first conductingstructure, to the final layer SS8 which contains the second conductingstructure. The cross-section of column [9′ may] 9′ can be definedarbitrarily via the selected electric field pattern. A number ofparallel conducting columns [may] can be generated by direct extensionof this procedure [and the]. The columns [may] can begin and end indifferent layers, such [this is apparent from] as shown in FIG. 5. In agiven layer which contributes [with] a conducting structure 9 inconnection with one or more conducting columns of vertical conductingstructures 9′, the latter shall be made concurrently with otherconducting 9 or semiconducting structures 10 which are patterned in thislayer, for instance, SS6 in FIG. 5[, i. e.] (i e, without having tocarry out other or different processing steps). Typically the degree ofconversion from a non-conducting to a conducting state or vice versa canbe controlled by the field strength and/or its time characteristics, andpossibly also by the duration of the field. Thus a column, whichconnects points in two different layers [may], can be formed such thatit functions as a resistor in a circuit by choosing the degree ofconductivity in segments from layer to layer along the column.

[0065] [A] Additionally, a method for erasing [electrical] electricallyconducting [or] and/or semiconducting structures generated in threedimensions forms a part of the invention.

[0066] In principle [may electrical] electrically conducting [or] and/orsemiconducting structures in single layers can be erased selectivelywith the use of EFGM20 as shown in any of the FIGS. 2a-f and suitablespectral modulation. [After] However, after joining [of] single layersinto a multilayer structure MLS, the erasing at time being can[,however,] only be performed globally [by the]. The multilayer structure,in case the matrix, is globally [is] subjected to an electric field withgiven field strength and/or characteristics and possibly adapted to thespecific response of the material to the energy supplied by the field.The materials in the matrix will then be reconverted until the matrix inits entirety arrives in an [electrical] electrically non-conductingstate[, something which will be]. This is the case if [it e. g.] thematrix is made of a material such as M (TCNQ). A multilayer structure ormatrix of M (MTCNQ) material may thereafter be reconfigured with new[electrical] electrically conducting [and] and/or semiconductingstructure, but this is not [at present] possible by using electricalfields according to prior art techniques. However, [a] another method[for generating] can be used as disclosed by the simultaneously filedInternational Patent Application PCT/N099/00023 which belongs to thepresent applicant[, may be used.].

[0067] [As] According to the present invention, the method forgenerating [according to the present invention makes possible] providesthat suitable materials [may] can be converted from an isolating to asemiconducting state or vice versa by electric fields, either directlyor indirectly [(e.g.](e.g., in the last instance due to a simultaneouslocal heating)[, it will be]. It is possible to apply the method tomanufacture [for instance] diodes and transistors [which may] that canbe connected electrically with resistances and capacitors to formcomplete active electronic circuits. More specific examples of activecomponents and circuits formed thereof shall be disclosed by thefollowing examples.

EXAMPLE 1

[0068]FIG. 6 shows a forward-biased pn junction diode with conductingand semiconducting structures generated [by the method] according to theinvention and [realised] realized in thin-film technology with foursublayers SS1-SS4. The layers SS2 and SS3 contain the activesemiconducting material provided between the [elctrodes] electrodes 11in [respectively the] sublayers SS1 and SS4, respectively. The activematerial 10 in [the] sublayer SS2 is an n-doped semiconductor, while theadjacent active material [10′ in the] 10′ in sublayer SS3 is a p-dopedsemiconductor. [ ]The electrodes 11 in the layers SS1 and SS4 arecontacted by horizontal [electrical] electrically conducting structuresor conducting paths 9 in the same layer. [The] Each separate layer inthe diode structure [in] of FIG. 6 [has] typically has a thickness ofabout 100 nm, such that the whole structure forms a multilayer structurewith a thickness less than 1 μm. The horizontal extension of the area ofthe diode structure will be determined by the spatial resolution [whichis realized with the use of an EFGM, but with] of an EFGM. However, itis possible to form electrodes 21, 22 of the electrode means E1, E2, asshown in FIGS., 2 a-f, [it will be possible to form electrodes 21,22]with pitches in the order of magnitude 0.2-1.0 μm [by]. These electrodescan be formed using conventional lithographic methods or by usingirradiation convertible materials and a method as disclosed in theabove-mentioned international patent application PCT/N099/00023. Specialprinting methods or use of anotechnological and chemical methods will[besides] be able to realize electrode structures [which] that are oneorder of magnitude smaller. Realistically [it may be supposed that] withthe available technologies for making the electrode devices it will bepossible to modulate point and line potentials spatially in twodimensions to a smallest extension of 0.1 μm.

EXAMPLE 2 MOSFET

[0069]FIG. 7 shows schematically a MOSFET for use in the presentinvention and realized wholly in organic material in thin-filmtechnology. The gate electrode 12 is provided in the sublayer SS1 andconnected with a horizontal conducting structure 9, while the sublayerSS2 constitutes the gate isolator 13. The active semiconducting material10 is provided in the sublayer SS3 and registers with the gate electrode10. The source and drain electrodes 14 are provided in the following toplayer SS4 and are contacted by horizontal [electrical] electricallyconducting structures 9 in the same layer. Each of the layers compriseseither [electrical] electrically conducting structures or asemiconducting structure, as well as dielectric areas. The thickness ofa MOSFET of this kind [may] can be ½ μm, while the extension in thehorizontal plane [such as may be realized with present technology will]can be from at most a few μ[m] m to less than 1 μm, cf. what is said inexample 1.

EXAMPLE 3 Logic CMOS Inverter

[0070] The MOSFET structure in FIG. 7 may now be used in logic gates,for instance a logic inverter in CMOS technology as shown in FIG. 8. Aninverter of this kind is formed by parallel connection of the drain andsource electrode in respectively an n-MOSFET and a p-MOSFET in aback-to-back configuration, with common gate electrode. For this purposea vertical conducting structure 15 is generated and passes through allsublayers SS1-SS7 and connects the electrodes 14′. The output signalfrom the inverter is conveyed on this conducting structure 15 to ahorizontal connecting structure 9 at left in the figure. The common gateelectrode 12 of the MOSFET [receive] receives the input signal via thehorizontal conducting structure 9 in the sublayer SS4 at right in theFIG. The thickness of all sublayers [will then be] is less than 1 μm,typically realized with about a thickness of about 0.7 μm, while thehorizontal extension of the inverter will have the same dimensions asstated above in connection with the discussion of the MOSFET structurein the FIG. 7.

EXAMPLE 4 CMOS AND Gate

[0071] Active components like the MOSFET structures shown in FIG. 7[may] can be used for forming integrated circuits by stacking [of] thesublayers with structures which have the desired electrical propertiesand wholly are realized in an organic thin-film technology.Specifically, the following example is [connected with] an AND gaterealized in CMOS technology with the use of the transistor structure asshown in FIG. 7. In order to facilitate the understanding of how activedevices such as field-effect transistors [may] can be combined inmultilayer structures and into functional devices [as], for instancelogic gates, reference shall be made to FIG. 9 [which]. FIG. 9 shows thecircuit diagram for an AND gate realized in complementary MOS technology(CMOS technology). The CMOS AND gate is realized with [respectively]n-MOSFETS and p-MOSFETS of the enrichment type as switches,respectively. Two input signals A and B are conveyed respectively to thegate electrodes on p-MOS Q₁ and Q₂ and the gate electrodes on n-MOS Q₃and Q₄. If both input signals switches A and B are high, the outputsignal {overscore (X)} will be low. In this case Q₃ and Q₄ will both beon and the p-MOS switches Q₁ and Q₂ will both off, [i.e.] i.e., nocurrent flows and the output signal {overscore (X)} hence goes low. If,on the contrary, either the input signal A or the input signal B is lowor both are low, [correspondingly] the p-MOS transistors Q₁[respectively], Q₂ will be switched on and the output signal {overscore(X)} goes high, [as] because either one or both of the seriallyconnected n-MOS transistors Q₃, Q₄ are off and no current flows. Thedevices Q₁ [.], Q₂, Q₃, Q₄ realize[, as will be seen,] a NAND gate [andto]. To realize an AND gate it is necessary to connect the output of theNAND gate with a logical inverter which also is realized in [ ]CMOStechnology[, respectively] with the use of a p-MOS switch Q₂ and ann-MOS Q₆ switch connected in parallel. This is a standard CMOS inverter[and if]. If its input signal {overscore (X)} is high, its output signalX [will be] is the [inverted] inverse of the input signal {overscore(X)} and hence low. Conversely a low input signal {overscore (X)} [willbe] is inverted to a high output signal X [and this]. This correspondsto the input signals A and B to the NAND gate both being high. [In otherwords it is easily realized that circuit as shown in FIG. 9 realizes anAND gate and] Circuits such as the AND gate shown in FIG. 9 can berealized with any number of inputs. Correspondingly, persons skilled inthe art will understand that [correspondingly] logic OR and NOR gates[may] can easily be realized [and with any number of inputs. However,in]. In principle, all Boolean functions can be realized in combinationsof one type of gate and one or more inverters realized in CMOStechnology, for instance, with the use of the transistor structure asshown in FIG. 7.

[0072] [Purely practically the] The AND gate can be implemented inthin-film technology as shown in FIGS. 10a-10 d and with the use ofMOSFET structures corresponding to that shown in FIG. 7. FIGS. 10a-10 dshow the AND gate wholly realized in thin-film technology [and] with theactive and passive devices provided in four sublayers SS1, SS3-SS5. Thefirst sublayer SS1 (FIG. 10a) contains the gate electrodes g₁-g₆ wherethe subscript points to the corresponding subscript for the MOSFETsQ₁-Q₆ in FIG. 9. The inputs A and B are conveyed to respectively thegate electrodes g₁, g₃ and g₂, g₄ and via horizontal conductingstructures or current paths 9. Correspondingly the gate electrodes g₅,g₆ in the inverter are connected with a horizontal current path 9. Avertical [electrical] electrically conducting structure is denoted as15[, the]. The symbol Δ [indicating] indicates that it extends upwardsin vertical direction from the sublayers SS1. In FIG. 10b, the symbols Δand ∇ indicate that the vertical conductor structure 15 in the layer SS3extend vertically through this layer and on both sides thereof. Thelayer SS3 comprises areas with active semiconductor materials b₁-b₆(corresponding to 10 in FIG. 7) which are assigned to and register withthe corresponding gate electrodes g₁-g₉ in the layer SS1. It is to beremarked that a layer SS2 [exclusively], apart from the verticalconductor structure 15 which also extends through this sublayer on bothsides thereof, exclusively consists of dielectric material which forms acommon gate isolator for the MOSFETs Q₁-Q₆ which realize the AND gate.The layer SS2 is[, of course,] located between SS1 and SS3, but has beenexcluded from the drawing. The layer SS4 in FIG. 10c is provided aboveand adjacent to the layer SS3 and comprises [respectively] the sourceelectrodes [S1-S6] S1-S6 and the drain electrodes d₁-d₆ for thecorresponding MOSFETs Q₁-Q₆. respectively. The active semiconductormaterial d₁-d₆ [which] that is located in [the] layer SS3 is hereindicated by stitched lines. The vertical current path 15 also extendsalso through the layer SS4 and to both sides thereof and contacts ahorizontal current path 9 in the sublayer SS5 as shown in FIG.. [IOd] 10d. This horizontal current path corresponds to the connection betweenthe drain electrodes d₂ and d₃ for the corresponding MOSFETs Q₂, Q₃ andis additionally also connected with the drain electrode d₁ on Q₁.Another horizontal current path 9 realizes the serial connection betweenthe source electrode [S3] s₃ on Q₃ and the drain electrode d₄ on Q₄. Thesource electrodes [S4] s₄ and [S6] s₆ are grounded over furtherhorizontal conductor structures 9, while the horizontal conductingstructure 9 farthest to right in the layer SS5 is supplied with avoltage V_(dd) and connects the source electrodes [S1, S2, S5 onrespectively] s₁, s₂, s₅ on Q₁, Q₂ and Q₅, respectively. A furtherhorizontal current path 9 uppermost in FIG. [IOd] 10 d forms theparallel connection between the drain electrodes d₅, d₆ on Q₅, Q₆ andthe output line, denoted with X. The output signal {overscore (X)} fromthe NAND gate consisting of Q₁, Q₂, Q₃, Q₄ is conveyed on the verticalcurrent path 15. FIG. 11 shows schematically how the layers in FIG. 10appear in stacked configuration[, the]. The layer SS2 [with](i e, thegate isolator [here being]) is included. [For] However, for the sake ofclarity the stack[, however,] is shown exploded in its separatesublayers SS1-SS5[, but] with correct registration [and the]. The courseof the vertical current path 15 through every sublayer is indicated bythe stitched line. With the gate electrode layer SS1-SS5 provided on anunderlying[, not shown] (not shown) dielectric layer, the total ANDstructure as shown in FIG. 11 may have a thickness of 0.75 μm and anarea of about 100 μm² (12-8 μm²). The volume of the structure will hencebe about 75 μm³. With conservative spatial resolution this implies thatabout [10 000] 10,000 logic gates of this kind [may] can be realized onan area of 1 mm² and with a thickness well below 1 μm. Correspondinglyscaled, the length of the current paths 9,15 together [becomes] is 60μm.

EXAMPLE 5 AND Gate with Vertically Stacked CMOS Circuits

[0073] A reduction of the current path length and a significantsimplification of the structure of the AND gate [may] can be achieved bystacking the MOSFET structures vertically as shown in FIG. 12. Again thesame reference numbers as in FIGS. 10 and 11 are used[, and it will]. Itcan be seen that the vertical AND gate structure exploits the fact thatthe gate electrodes g₁ and g₃ of the transistors Q₁, Q₃ are at the samecommon potential, the gate electrodes g₂ and g₄ in Q₂. Q₄ on anothercommon potential and the gate electrodes g₅ and g₅ in Q₆ on a thirdcommon potential. Hence the transistors Q₁-Q₆ are [implemented]implemented as [ ]CMOS circuits in a pairwise back-to-back configurationby common gate electrode g₁, g₃; g₂, g₄; g₅. g₆ for the correspondingMOSFET structures Q₁, Q₃; Q₂, Q₄; Q₅, Q₆. Each CMOS circuit is providedon an isolating layer, which in FIG. 12 is located below Q₃, between Q₁and Q₄ and between Q₂ and Q₅ in each of the MOSFET structures. The gateelectrodes g are also, of course, isolated from the active semiconductormaterial b [by], not explicitly denoted as isolating layers whichcomprise the respective gate isolators. The horizontal current paths inFIGS. 10 and 11 are now substantially replaced by vertical current pathswhich extend through the layers and provide the same connection as shownin the equivalent circuit in FIG. 9. Particularly the current path 15 isshown which also is realized vertically in the configuration in FIG. 10and[, as will be seen,] as before connects the gate electrodes g₅, g₆ onQ₅, Q₆ with the connection between the drain electrodes d₂, d₃ on Q₂, Q₃and the drain electrode d₁ on Q₁,

[0074] The vertical AND gate structure in FIG. 12 including thesubstrate 1 is generated by a total of 24 sublayers, of which 6relatively thick isolating layers form the gate isolators and threecorresponding thick isolating layers isolate the paired combinations ofMOSFET structures mutually. With the same dimensions as indicated inconnection with the description of FIG. 1, the whole stacked layerconfiguration in FIG. 12 [hence will have] has a thickness of about 3.0μm and can be provided on an area of 16 μm². The total volume thusbecomes less than 50 μm³, a reduction of the volume of ⅓ relative to theconfiguration in FIG. 11. [Most] However, most important is[, however,]the reduction in the length of the current paths [which in]. In theconfiguration in FIG. 11 from the indicated dimensions [will] thecurrent paths have a length of 52 μm[, may in]. In the configuration inFIG. 12 [well be], the current length is about 15 μm in an optimalembodiment, which implies a reduction of about 70%. [In this connectionit shall particularly be taken in regard that] Note, FIG. 12 isschematic and [that] the vertical current paths arc mutually displacedin the horizontal plane in order to appear more clearly. They may,however, lie in the same plane, parallel to one of the side surfaces ofthe structure.

[0075] Within the scope of today's thin-film technology and usingtechnologies as mentioned above in order to create [electrical]electrically conducting [and] and/or semiconducting structures in thinfilms by irradiation of convertible organic materials, it is whollypossible to reduce the linear dimensions in the horizontal direction,such that the component density [may] can be increased by at least oneorder of magnitude. This implies that the configuration in FIG. 11 mayrealize about 10⁵ logic gates of the kind shown on 1 mm² [and] with alayer thickness well below 1 μm[, while]. Additionally, theconfiguration in FIG. 12 might realize about [6-105] 6·10⁵ gates on thesame area with a somewhat better form factor, such that the increase inthe device density becomes about 33% relative to the device density ofthe configuration in FIG. 11.

[0076] The processing of single layers[, i. e. the generating ofelectrical conducting and semiconducting structures may] (i.e., thegenerating of electrically conducting and/or semiconducting structures)may include possible post-treatments and corrections, e.g., a possibleheat treatment before the separate layers are joined into a multilayerstructure and form a stacked circuit configuration after the convertingby means of electric fields has taken place and when it is performed asshown in FIGS. 2a-f and FIG. 3 [, include possible post-treatments andcorrections, e. g. a possible heat treatment before the separate layersare joined into a multilayer structure and form a stacked circuitconfiguration.].

[0077] [For instance]For instance, after the conversion a heat treatmentof single layers [after the conversion may] can be performed to controlconducting or semiconducting properties, [e. g.] e.g., conversion ofmonomer to oligomer or polymer, doping, crystallization, etc. Suchprocesses are well-known and have a wide application [and]. Therefore,specific examples [shall hence not be given here. The] are not provided.For example, the heat treatment may [e.g.] be performed by means ofirradiation. Another possibility is to use the electric alternatingfields. In principle alternating fields may also be used to effect thefield conversion of EFCM [and]. Then, the power supply 23 shown in FIGS.2a-f [must then, of course, be] is an alternating voltage source. [Inthat connection it shall be remarked that a] A resistive material, whichis subjected to an alternating field, will be heated. By using analternating voltage field for generating a transition from anon-conducting to [for instance] a conducting and/or semiconductingstate, a heating of the thus generated [electrical] electricallyconducting structure may take place and a possible desired heattreatment may also take place in situ and simultaneously with theconversion process.

[0078] [By for instance] For example, by using organic materials in thelayers and generating the [electrical] electrically conducting [and]and/or semiconducting structures with conversion [and] by means ofelectric fields according to the present invention, [it may be obtained]a far simpler and [cheaper] less expensive manufacturing of electronicdevices is obtained than [which] is possible with today's inorganicsemiconductor technology. If a reel-to-reel arrangement is used in themanufacture of circuits as shown in FIG.. [7,] 3, the production [may]can take place with high volume and high speed and without essentialdimensional limitations. With the joining of separate layers into amultilayer structure and forming of a stacked configuration, theregistration between the layers will[, however,] be critical [amongother] in order to ensure that vertical conducting structures inseparate layers register mutually [and that for instance electrodes].Electrodes and active semiconductor materials in the semiconductorstructures [do the same] also need to register mutually. The requirementfor registration accuracy [will be] is given by the pitch [which may]that can be realized in the manufacture of the [electrical] electricallyconducting [and] and/or semiconducting structures, but may practicallyalso be realized by using interferometric methods for control andpositioning, optically recordable marking, or mechanical or electricalnanotechnology. Such measures, however, fall outside the scope of thepresent invention and are hence not discussed in greater detail, butmust be regarded as known to persons skilled in the art.

[0079] By using the method for generation according to the presentinvention, the protocol for a given circuit configuration in multilayerdesign [may] can be generated far from the manufacturing location of thecircuit [and transmitted thereto]. For example, the protocol can betransmitted to the manufacturing location for downloading to [forinstance] a control device [which] that controls the generation of thephysical circuit patterns in situ at the manufacturing location. [A]Thus, a user [may hence thereby] can generate and produce circuits bytele-processing according to the user's own specifications solely bytransmitting the necessary instructions and information. [The] Thereby,the present invention [may thus furnish] furnishes the conceptapplication- and customer-specific circuit production with a radicallynew content.

10. (Amended) An electric field genetor/modulator (EFGM) for patterning and generating electrically conducting and/or semiconducting structures in tow or three dimensions in a composite matrix, wherein the matrix comprises one or more materials respectively provided in one or more spatially separate and homogenous material structures, wherein the materials in response to the supplied energy can undergo specific physical and/or chemical changes of state which cause transition from an electrically non-conducting state to an electrically conducting and/or semiconducting state and vice versa, or a change in the conduction mode of the material, wherein each material structure is made in the form of a thin layer, and wherein the electric field generator/modulator comprises: a first electrode means with a plurality of parallel strip electrode provided in a first plane; a second electrode means with a plurality of parallel strip electrodes provided at a distance from the first electrode means and super-positioned thereto in a second plane parallel with the first plane such that the electrodes mutually are substantially orthogonally oriented in a matrix-like arrangement; wherein the electrode means over cross-connection devices are connected with a controllable power supply; and wherein a space between each electrode means is agapted to receive a thin-film material in a form of a discrete component or a continuous tape, which continuously or intermittently is fed through the space without touching the electrode means and with simultaneous positioning and alignment spaced apart from and between each electrode means in a plane substantially parallel thereto, whereby the electrically conducting and/or semiconducting structures are optionally generated according to a determined protocol and are generated by means of point, line and/or area potentials that are created between selected electrodes in the electrode means when the selected electrodes over the cross-connection devices are suppled with electric power.
 11. (Amended) The electric field generator/modulator according to claim 10, wherein the electrodes in each electrode means is provided on or in surfaces of respective substrates facing each other.
 12. (Amended) The electric field generator/modulator according to claim 11, wherein the strip electrodes are made as a part of the substrates and form conducting structures in the substrates.
 13. (Amended) The electric field generator/modulator according to claim 10, wherein the distance between the electrode means is controllable depending on a thickness of the thin-film material.
 14. (Amended) The electric field generator/modulator according to claim 10, wherein the electrodes in each electrode means are provided with a mutual distance between 0.1 μm and 1.0 μm.
 15. (Amended) The electric field generator/modulator accoding to claim 10, wherein the electrodes in each electrode means are formed with substantially constant width of 0.1 μm to 1.0 μm. 